Instruction pipelining is a way to overlap the steps involved in executing multiple instructions. This lesson introduces the pipeline model, its stages, and the relationship between pipelining, throughput, and latency.
A processor executes instructions by performing a sequence of operations. In a simple model, these operations include fetching an instruction, decoding it and obtaining its operands, executing it, accessing memory when needed, and writing a result back to a register.
All flashcards
What is instruction pipelining?
A processor technique that divides instruction execution into sequential stages and overlaps the stages of multiple instructions.
What are the five classic RISC pipeline stages?
Instruction fetch, instruction decode and register fetch, execute, memory access, and register write-back.
What is the role of pipeline registers?
They hold instruction data and intermediate results between stages so that each stage can pass its work to the next.
How do throughput and latency differ?
Throughput is the rate at which instructions complete. Latency is the time an individual instruction takes to pass through the required processing.
What is a fully pipelined processor?
A processor capable of fetching a new instruction every cycle, assuming no condition is delaying instruction fetch.
Quiz questions
What is the main purpose of instruction pipelining?Answer: To overlap stages of multiple instructions so different processor units can work concurrently.
What does a pipeline register do?Answer: It stores instruction information and intermediate results between pipeline stages.
In the classic five-stage RISC pipeline, which stage normally stores a result in a register?Answer: Register write-back.
A full pipeline ideally completes about one instruction per cycle. Which performance measure does this describe?Answer: Throughput.
Why can increasing pipeline depth allow a processor to use a higher clock frequency?Answer: Each stage may perform less work, allowing its logic to complete in less time.