This lesson introduces out-of-order execution and contrasts it with the simpler in-order approach. Understanding the difference explains how modern processors keep their execution units productive while waiting for data.
A program presents instructions in a particular sequence called program order. In a basic in-order processor, instructions are fetched and handled in that sequence. A typical instruction cycle includes fetching an instruction, waiting until its input operands are available, executing it, and writing its result back to the register file.
All flashcards
Out-of-order execution
A scheduling approach that lets ready instructions execute before older instructions that are waiting, while preserving correct architectural behavior.
Register renaming
Mapping architectural register names to physical storage locations to remove false WAW and WAR dependencies.
Precise exception
An exception that leaves visible processor state consistent with a specific point in program order.
Speculative execution
Performing work based on a prediction or provisional assumption before it is known to be correct.
Tomasulo's algorithm
A scheduling approach using register renaming and reservation stations to hold instructions until they are ready.
Quiz questions
In an out-of-order pipeline, what distinguishes dispatch from issue?Answer: Dispatch places an instruction in a waiting structure; issue sends a ready instruction to an execution unit.
Which dependencies can register renaming remove?Answer: False WAW and WAR dependencies caused by reuse of architectural register names.
Which scheduling mechanism was used by the CDC 6600?Answer: A scoreboard that tracked conflicts and scheduled instructions.
What should a processor do with younger speculative work after a branch prediction proves incorrect?Answer: Discard or undo the speculative work and restart from the correct control-flow point.
What is a potential cost of increasing the capacity of instruction queues and buffers?Answer: Greater hardware cost and potentially more work lost after a branch misprediction.